The present invention relates in general to switched capacitor circuits and in particular to methods and circuits for compensating for finite common mode rejection in switched capacitor circuits.
One particular technique for performing analog to digital (A/D) conversion is through successive approximation. The basic successive approximation A/D converter (ADC) includes an analog comparator and a clocked feedback loop having a successive approximation register (SAR) and a digital to analog converter (DAC).
Generally, the analog input signal voltage is sampled onto an array of weighted capacitors, during the sampling phase, the top plates of which are coupled to one comparator input. The other comparator input is coupled to a comparison voltage, which could be a fixed reference voltage in a single-ended system or the voltage at the top plates of second capacitor array in a differential system.
During the first clock cycle of the subsequent conversion phase, the bottom plate of the capacitor representing the digital MSB is coupled to a reference voltage while the bottom plates of the remaining capacitors in the array are coupled to ground or a second reference voltage (ground will be assumed here). The new top plate voltage appears at the input of the comparator and is compared against the comparison voltage. If the new top plate voltage is below the comparison voltage, then the MSB is xe2x80x9ckeptxe2x80x9d by the SAR in the feedback loop by maintaining its bottom plate coupled to the reference voltage. On the other hand, if the top plate voltage is above the comparison voltage, the SAR couples and the bottom plate of the MSB capacitor to ground. The state of the MSB capacitor represent the MSB of the digital output word as a Logic 1. The bottom plate of the second MSB is then coupled to the reference voltage and the same test is performed to determine the state of the next digital code bit. The successive approximation algorithm continues by repeating this procedure for the remaining capacitors in the array such that the voltage difference at the inputs to the comparator converge to zero. At the end of this bit cycling process, the configuration of the switches coupling the bottom plates either to Vref or Gnd represents the input sample in digital form.
Successive approximation A/D converters are useful a wide range of applications, including data acquisition, test equipment, instrumentation, cellular communications, among others. Notwithstanding, in order to improve and broaden the utility of this type of A/D converter, significant challenges remain to be addressed. These challenges include improving the device speed given a set of process constraints, reducing the coding error rate, handling metastable states and device calibration
In accordance with the inventive concepts, circuits and methods are disclosed for compensating for a finite common mode rejection in switch capacitor circuitry. Such circuits and methods are particularly useful in circuitry such as charge redistribution analog to digital converters, although not necessarily limited thereto.
According to one embodiment of the inventive concepts, a method is disclosed for compensating for finite common mode rejection in a switched capacitor circuit including arrays of input capacitors coupled to first and second differential nodes. A common mode voltage is sampled onto the differential nodes during a sampling phase. Next, the input capacitors are coupled to a ground node against which the common mode voltage is referenced to capture an offset voltage between the first and second differential nodes. The voltage offset is then subtracted out.
Advantageously, any voltage offset caused by the finite common mode rejection of the input capacitor arrays at a given common mode voltage in a switch capacitor circuitry can easily be compensated for. With respects to circuits and systems including a comparator or similar operational amplifier circuit also introducing an input offset voltage, both the offset caused by the finite common mode rejection and that caused by the operational amplifier circuit can be subtracted out simultaneously. This feature is particularly useful in a charge redistribution analog to digital converters where an input voltage offset, no matter the source, can cause errors in the digital encoding.